With increasing demands for embedded memory type structures, mixed-signal circuits, and system on chip (SOC) IC design, it has become necessary to form multiple transistor structures on a single die to achieve integrated functioning of the different transistor structures. For example, transistors with different structures and functions typically operate under different current and voltage parameters requiring different LDD widths and depths for the various transistors.
As MOSFET device characteristic sizes are scaled down below 0.25 microns, including below 0.1 micron, device designs must be modified for each generation of device scaling. For example, short channel effects (SCE) are one of the most important challenges for designers to overcome as device critical dimensions are scaled down. Among the many manifestations of SCE, are Voltage threshold (VT) rolloff, drain induced barrier lowering (DIBL), and subthreshold swing variation.
In addition, there is an increasing demand for integrating mixed signal (i.e., digital/analog) functions on a single chip, e.g., system on chip (SOC devices, thereby requiring the formation of different types of transistors. Problematically, transistors for analog circuits have significantly different operating and processing requirements compared to transistors for digital or logic circuits.
Digital CMOS transistors are primarily concerned with increasing drive current while reducing short channel effects (SCE), thereby requiring relatively high implant doses in pocket implants to improve device operation. On the other hand, analog CMOS devices are degraded by such processing approaches including transistor Voltage threshold (VT) matching and Voltage gain characteristics.
Methods for dealing with the different processing requirements in forming different types of transistors (i.e. analog and digital) on a single chip, e.g., SOC devices, have focused on separate processes carried out for each type of transistor. Such prior art approaches lead to higher costs and process incompatibility which detrimentally impacts the performance and reliability of both transistor types.
There is therefore a need in the semiconductor device integrated circuit manufacturing art for an improved mixed signal device and method for forming the same such that digital and analog CMOS devices may be more effectively individually optimized for performance and reliability in parallel production processes, including forming system on chip (SOC) devices.
It is therefore an object of the present invention to provide an improved mixed signal device and methods for forming the same such that digital and analog CMOS devices may be more effectively individually optimized for performance and reliability in parallel production processes, including forming system on chip (SOC) devices, as well as overcoming other shortcomings of the prior art.